The present invention relates to the testing of modern electronics systems, and more particularly to a hardware architecture for use in testing a complicated modern electronics system, and even more particularly to an integrated circuit testing device for use in testing a complicated modern electronics system.
An important part of the operation of many electronics systems is the ability to detect when it is not operating properly. In addition to detecting the presence of faults, it is an additional requirement in many systems that the ability to determine the location of the fault be provided, in order to facilitate repairs to the system.
An earlier method of detecting faults in an electronics system was to build redundant circuits into the hardware. When such a system is working properly, the outputs of the redundant circuits will match one another. A mismatch in the outputs of such identical circuits indicates that at least one of them is not working properly. In some systems, where it was also necessary to determine which of the redundant circuits was malfunctioning, three or more such redundant circuits were provided. Then, any one circuit whose output differed from the remaining redundant circuits was easily identified as the malfunctioning circuit.
Another approach to fault isolation and detection is to build into the system special hardware which, during a "test mode of operation," applies sequences of stored signals to what are normally the input nodes of the circuit under test (CUT), and then compares the actual outputs of the CUT with pre-stored, expected responses. By carefully selecting a sequence of test input signals, it is often possible not only to detect the presence of a fault, but also to determine the location of the faulty circuit element.
The above-described built-in test (BIT) "functional" approaches to fault detection and isolation have a number of drawbacks, including the great deal of time that is necessary to develop the tests, as well as the need to dedicate much hardware to support these and other "ad hoc" test methods. Also, as the number of circuits on integrated circuits ("chips"), circuit boards and total systems gets larger and larger, the ability of the "functional" test approach to locate circuit faults decreases because this increase in circuit density has not been matched by a comparable increase in input and output (I/O) pins to the respective chip, board or system. Consequently, it may not be possible to produce a pattern of input signals which will determine, with any certainty, which one of a number of circuits is failing.
An alternative, and more robust solution to the problem of testing electronic systems is the so-called "structured" BIT approach. In this test approach, known input signals are applied, and output signals are monitored not only at the I/O interface of a circuit, but also at particular nodes within the circuit which are not normally accessible to non-circuit elements during normal operation of the system. As a minimum, this approach to testing the primary circuits of a system requires the addition of special test circuits in order to provide access to the internal nodes of the primary circuits. In addition, it is common to include within the system dedicated hardware whose function is to perform the tests. The test itself may comprise the application of specially devised signal patterns and/or random signal patterns at the control points in order to propagate potential faults to the built-in observation points. The signal patterns detected at these observation points may be compressed, using known data compression techniques, and then compared to stored, expected responses.
Even with the use of "structured" BIT hardware, modern complex systems pose testability problems. This stems from the fact that a complex system very often comprises a number of physically separate circuit boards which are interconnected by means of a common backplane to form a chassis. In addition, it is possible for a system to comprise more than one chassis, thus creating the need for inter-chassis test operations and coordination.
Testing requirements for such systems typically may include the detection of at least 95% of all faults, as well as the ability to isolate at least 90% of all detectable faults to a single circuit card, which can then be replaced by a technician having minimal training. To achieve these testability requirements, BIT systems typically require dedicated communication paths which allow the test hardware to communicate even when the primary system communication paths are faulty. Several test busses have been standardized in the past few years in order to serve this purpose.
One of these is the IEEE Standard 1149.1 test bus, which provides a simple, serial data and instruction transfer bus. It is a single-ended, 4-wire bus for transferring a clock, data in, data out, and control signals. With this bus, devices are interconnected in a serial, daisy-chain fashion, so that data is clocked into and out of each connected device in succession, in a process that is referred to as "scanning" of data. Many off-the-shelf parts now contain an interface to the IEEE Standard 1149.1 bus.
Another standard test bus is the proposed IEEE Standard 1149.5 test bus. This bus is defined as four single-ended wires: two data lines (like the IEEE Standard 1149.1 bus described above), and two bi-directional control lines which allow multi-master capability. This bus allows a number of interfaces to be tied together on the same four wires in a party-line fashion, so that there can be one sender and multiple simultaneous listeners.
Several testing approaches have been used in the kind of multi-board, multi-chassis systems described above. One of these approaches is to use a testing processor, located on one of the circuit boards, to perform all of the testing for the chassis. Using only the one testing processor for testing all of the circuit boards makes it possible to generate circuit failure information of the type which can be culled only from an analysis of which boards are failing and which ones are not. This technique requires that a test bus, such as the IEEE Standard 1149.1 test bus described above, be routed not only to the BIT logic located on the same board as the testing processor, but also through the backplane so that the BIT logic located on other boards can be controlled.
The method of using a single processor to entirely control chassis testing has the drawback, however, that if a circuit board from the chassis is to be removed and then reinstalled in the backplane of another chassis, it does not take with it any of the original testing processor's control logic for testing its own circuits. Instead, this must be at least reproduced, and probably redesigned (depending on the logic involved), in the testing processor of the new chassis. Another drawback is the fact that a historical record of faults that have occurred on the board in the original chassis (i.e., a "fault log") does not travel with the circuit board, but instead stays with the processor still located on the original chassis. Consequently, this important information is essentially lost when the board is removed from its original environment. Finally, yet another drawback of this test approach is that it should not be used in a multi-chassis environment. This is because a test bus such as the IEEE Standard 1149.1 test bus should not cross from one backplane to another because it is a single ended logic signal (high quality interface standards recommend the use of only differential signals between backplanes).
An alternative testing approach is to equip each circuit board with a testing processor and a "private" test bus, such as an IEEE Standard 1149.1 test bus. With this arrangement, each circuit board is responsible for its own testing. An advantage of this is that the board's test capability moves with the board if it is to be reinstalled in a different chassis. Another advantage is that the circuit board's fault log also travels with the board, so the new chassis gets the benefit of testing which was performed on the board in the original chassis. However, because each board's testing processor operates independently of other testing processors, it is not possible, with this approach, to get the benefit of correlating test results from all of the boards in the system.